My track record of success is reflected in my 60+ peer-reviewed publications, 600+ citations, and at date (February 2023), according to Google Scholar I have a h-index of 15 and i10-index of 22, respectively.

PhD Thesis

  • Casale-Brunet, S., (2015), “Analysis and optimization of dynamic dataflow programs”, Ecole Polytechnique Fédérale de Lausanne EPFL, STI Electrical and Electronics School of Engineering, Switzerland.

Peer-Reviewed Journals

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2022), “Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis”, Journal of Low Power Electronics and Applications, 12(3), 40.

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2022), “Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution”, Journal of Low Power Electronics and Applications, 12(3), 36.

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2021), “Methodologies for Synthesizing and Analyzing Dynamic Dataflow Programs in Heterogeneous Systems for Edge Computing”, IEEE Open Journal of Circuits and Systems, 2, 769-781.

  • Prihozhy, A., Casale-Brunet, S., Bezati, E., Mattavelli, M., (2020), “Pipeline synthesis and optimization from branched feedback dataflow programs”, Journal of Signal Processing Systems, 92, 1091-1099.

  • Casale-Brunet, S., Mattavelli, M., (2018), “Execution trace graph of dataflow process networks”, IEEE Transactions on Multi-Scale Computing Systems, 4(3), 340-354.

  • Michalska, M., Casale-Brunet, S., Bezati, E., Mattavelli, M., (2017), “High-precision performance estimation for the design space exploration of dynamic dataflow programs”, IEEE Transactions on Multi-Scale Computing Systems, 4(2), 127-140.

  • Michalska, M., Bezati, E., Casale-Brunet, S., Mattavelli, M., (2016), “A partition scheduler model for dynamic dataflow programs”, Procedia Computer Science, 80, 2287-2291.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J., (2016), “Clock-gating of streaming applications for energy efficient implementations on FPGAs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(4), 699-703.

  • Sau, C., Meloni, P., Raffo, L., Palumbo, F., Bezati, E., Casale-Brunet, S., Mattavelli, M., (2016), “Automated design flow for multi-functional dataflow-based platforms”, Journal of Signal Processing Systems, 85, 143-165.

  • Michalska, M., Casale-Brunet, S., Bezati, E., Mattavelli, M. (2015), “Execution trace graph based multi-criteria partitioning of stream programs”, Procedia Computer Science, 51, 1443-1452.

  • Canale, M., Casale-Brunet, S., (2014), “A multidisciplinary approach for Model Predictive Control Education: A LEGO Mindstorms NXT-based framework”, International Journal of Control, Automation and Systems, 12, 1030-1039.

  • Casale-Brunet, S., Elguindy, A., Bezati, E., Thavot, R., Roquier, G., Mattavelli, M., Janneck, J., (2013), “Methods to explore design space for MPEG RMC codec specifications”, Signal Processing: Image Communication, 28(10), 1278-1294.

Peer-Reviewed Conference Papers

  • Casale-Brunet, S., Zichichi, M., Hutchinson, L., Mattavelli, M., Ferretti, S., (2022), “The impact of NFT profile pictures within social network communities”, In Proceedings of the 2022 ACM Conference on Information Technology for Social Good (pp. 283-291). ACM.

  • Casale-Brunet, S., Ribeca, P., Alberti, C., Ozturk, U., Mattavelli, M., (2022), “A Benchmark of Entropy Coders for the Compression of Genome Sequencing Data”, In 2022 Data Compression Conference (DCC) (pp. 01-01). IEEE.

  • Ozturk, U., Casale-Brunet, S., Ribeca, P., Mattavelli, M, (2022), “MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments”, In 2022 Data Compression Conference (DCC) (pp. 478-478). IEEE.

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2021), “SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis”, In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (pp. 62-68). IEEE.

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2021), “Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms”, In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (pp. 69-76). IEEE.

  • Casale-Brunet, S., Ribeca, P., Doyle, P., Mattavelli, M., (2021), “Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem”, In 2021 IEEE International Conference on Blockchain (Blockchain) (pp. 188-195). IEEE.

  • Bloch, A., Casale-Brunet, S., Mattavelli, M., (2021), “Inter-actions parallel execution on GPU from high-level dataflow synthesis”, In 2021 55th Asilomar Conference on Signals, Systems, and Computers (pp. 1151-1155). IEEE.

  • Bezati, E., Casale-Brunet, S., Mosqueron, R., Mattavelli, M., (2019), “An heterogeneous compiler of dataflow programs for ZYNQ platforms”, In ICASSP 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 1537-1541). IEEE.

  • Prihozhy, A., Casale-Brunet, S., Bezati, E., Mattavelli, M., (2018), “Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines”, In 2018 IEEE International Workshop on Signal Processing Systems (SiPS) (pp. 1-6). IEEE.

  • Modas, A., Casale-Brunet, S., Stewart, R., Bezati, E., Ahmad, J., Mattavelli, M., (2018), “Shared-variable synchronization approaches for dynamic data flow programs”, In 2018 IEEE International Workshop on Signal Processing Systems (SiPS) (pp. 263-268). IEEE.

  • Casale-Brunet, S., Schuepbach, T., Guex, N., Iseli, C., Bridge, A., Kuznetsov, D., Sigrist, C., Lemercier, P., Xenarios, I., Bezati, E., (2018), “Towards in the field fast pathogens detection using FPGAs”, In 2018 28th International Conference on Field Programmable Logic and Applications (FPL) (pp. 463-4631). IEEE.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., (2017), “Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs”, In 2017 51st Asilomar Conference on Signals, Systems, and Computers (pp. 494-498). IEEE.

  • Casale-Brunet, S., Bezati, E., Bloch, A., Mattavelli, M., (2017), “Profiling of dynamic dataflow programs on MPSoC multi-core architectures”. In 2017 51st Asilomar Conference on Signals, Systems, and Computers (pp. 504-508). IEEE.

  • Casale-Brunet, S., Bezati, E., Mattavelli, M., (2017), “Design space exploration of dataflow-based Smith-Waterman FPGA implementations”, In 2017 IEEE International Workshop on Signal Processing Systems (SiPS) (pp. 1-6). IEEE.

  • Michalska, M., Bezati, E., Casale-Brunet, S., Mattavelli, M., (2017), “Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms”, In 2017 25th European Signal Processing Conference (EUSIPCO) (pp. 1339-1343). IEEE.

  • Casale-Brunet, S., Bezati, E., Mattavelli, M., (2017), “High level synthesis of Smith-Waterman dataflow implementations”, In 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 1173-1177). IEEE.

  • Michalska, M., Casale-Brunet, S., Bezati, E., Mattavelli, M., Janneck, J. (2016), “Trace-based manycore partitioning of stream-processing applications”, In 2016 50th Asilomar Conference on Signals, Systems and Computers (pp. 422-426). IEEE.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J., (2016), “High-level system synthesis and optimization of dataflow programs for MPSoCs”, In 2016 50th Asilomar Conference on Signals, Systems and Computers (pp. 417-421). IEEE.

  • Michalska, M., Ahmad, J., Bezati, E., Casale-Brunet, S., Mattavelli, M., (2016), “Performance estimation of program partitions on multi-core platforms”, In 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (pp. 1-8). IEEE.

  • Michalska, M., Casale-Brunet, S., Bezati, E., Mattavelli, M., (2016), “High-precision performance estimation of dynamic dataflow programs”, In 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) (pp. 101-108). IEEE.

  • Casale-Brunet, S., Bezati, E., Mattavelli, M., (2016), “Programming models and methods for heterogeneous parallel embedded systems”, In 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC) (pp. 289-296). IEEE.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J., (2016), “High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms”. In 2016 International conference on embedded computer systems: Architectures, modeling and simulation (SAMOS) (pp. 227-234). IEEE.

  • Janneck, J., Cerdersjö, G., Bezati, E., Casale-Brunet, S., (2014), “Dataflow machines. In 2014 48th Asilomar Conference on Signals”, Systems and Computers (pp. 1848-1852). IEEE.

  • De Saint Jorre, D., Alberti, C., Mattavelli, M., Casale-Brunet, S., (2014), “Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms”, In 2014 IEEE International Conference on Image Processing (ICIP) (pp. 2115-2119). IEEE.

  • Canale, M., Casale-Brunet, S., Bezati, E., Mattavelli, M., Janneck, J., (2014), “Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling”, In 2014 IEEE Workshop on Signal Processing Systems (SiPS) (pp. 1-6). IEEE.

  • Casale-Brunet, S., Wiszniewska, M., Bezati, E., Mattavelli, M., Janneck, J., Canale, M., (2014), “TURNUS: An open-source design space exploration framework for dynamic stream programs”, In Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (pp. 1-2). IEEE.

  • Casale-Brunet, S., Bezati, E., Mattavelli, M., Canale, M., Janneck, J., (2014), “Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control”, In Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (pp. 1-6). IEEE.

  • Janneck, J., Casale-Brunet, S., Mattavelli, M., (2014), “Characterizing communication behavior of dataflow programs using trace analysis”, In 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) (pp. 44-50). IEEE.

  • Sau, C., Raffo, L., Palumbo, F., Bezati, E., Casale-Brunet, S., Mattavelli, M., (2014), “Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case”, In 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV) (pp. 59-66). IEEE.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J., (2014), “Coarse grain clock gating of streaming applications in programmable logic implementations”, In Proceedings of the 2014 electronic system level synthesis conference (ESLsyn) (pp. 1-6). IEEE.

  • Ab Rahman, A., Casale-Brunet, S., Alberti, C., Mattavelli, M., (2014), “A methodology for optimizing buffer sizes of dynamic dataflow FPGAa implementations”, In 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) (pp. 5003-5007). IEEE.

  • Casale-Brunet, S., Bezati, E., Alberti, C., Mattavelli, M., Amaldi, E., Janneck, J., (2013), “Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications”, In 2013 Asilomar Conference on Signals, Systems and Computers (pp. 1796-1800). IEEE.

  • Casale-Brunet, S., Mattavelli, M., Alberti, C., Janneck, J., (2013), “Systems design space exploration by serial dataflow program execution”, In 2013 Asilomar Conference on Signals, Systems and Computers (pp. 1805-1809). IEEE.

  • Casale-Brunet, S., Bezati, E., Alberti, C., Mattavelli, M., Amaldi, E., Janneck, J., (2013), “Partitioning and optimization of high level stream applications for multi clock domain architectures”, In SiPS 2013 Proceedings (pp. 177-182). IEEE.

  • Ab Rahman, A., Casale-Brunet, S., Alberti, C., Mattavelli, M., (2013), “Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H. 264 decoder implementation case study”, In 2013 Conference on Design and Architectures for Signal and Image Processing (pp. 63-70). IEEE.

  • Casale-Brunet, S., Bezati, E., Alberti, C., Roquier, G., Mattavelli, M., Janneck, J., Boutellier, J., (2013), “Design space exploration and implementation of RVC-CAL applications using the TURNUS framework”, In 2013 Conference on Design and Architectures for Signal and Image Processing (pp. 341-342). IEEE.

  • Casale-Brunet, S., Alberti, C., Mattavelli, M., Janneck, J. (2013), “Turnus: a unified dataflow design space exploration framework for heterogeneous parallel systems”, In 2013 Conference on Design and Architectures for Signal and Image Processing (pp. 47-54). IEEE.

  • Casale-Brunet, S., Alberti, C., Mattavelli, M., Janneck, J., (2013), “Design space exploration of high-level stream programs on parallel architectures”, In Conference: 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013).

  • Canale, M., Casale-Brunet, S., (2013), “A Lego Mindstorms NXT experiment for model predictive control education”, In 2013 European Control Conference (ECC) (pp. 2549-2554). IEEE.

  • Casale-Brunet, S., Mattavelli, M., Alberti, C., Janneck, J., (2013), “Representing guard dependencies in dataflow execution traces”, In 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (pp. 291-295). IEEE.

  • Bezati, E., Casale-Brunet, S., Mattavelli, M., Janneck, J., (2013), “Synthesis and optimization of high-level stream programs”, In Proceedings of the 2013 Electronic System Level Synthesis Conference (ESLsyn) (pp. 1-6). Ieee.

  • Casale-Brunet, S., Mattavelli, M., Janneck, J., (2013), “Turnus: A design exploration framework for dataflow system design”, In 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 654-654). IEEE.

  • Casale-Brunet, S., Mattavelli, M., Janneck, J., (2013), “Buffer optimization based on critical path analysis of a dataflow program design”, In 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1384-1387). IEEE.

  • Casale-Brunet, S., Mattavelli, M., Alberti, C., Janneck, J., (2013), “Systems Design Space Exploration by Serial Dataflow Program Executions”, In 47th Annual Asilomar Conference on Signals, Systems, and Computers, 2003.

  • Casale-Brunet, S., Alberti, C., Mattavelli, M., Janneck, J., (2013), “Design space exploration of high level stream programs on parallel architectures: a focus on the buffer size minimization and optimization problem”, In 2013 8th International Symposium on Image and Signal Processing and Analysis (ISPA) (pp. 738-743). IEEE.

  • Ab Rahman, A. A. H., Thavot, R., Casale-Brunet, S., Bezati, E., Mattavelli, M., (2012), “Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program”, In Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing (pp. 1-8). IEEE.

  • Casale-Brunet, S., Mattavelli, M., Janneck, J., (2012), “Profiling of dataflow programs using post mortem causation traces”, In 2012 IEEE Workshop on Signal Processing Systems (pp. 220-225). IEEE.